Notch filters are often used to remove unwanted signal components within a specific frequency range for a particular circuit. One application for a notch filter is in chopper stabilized Hall effect sensors, in which a notch filter, sometimes referred to as a sinc filter, may be used to remove unwanted components, such as a modulated offset signal component which arises as ripple, that result from the chopping operation without requiring a multi-pole filter approach that may result in unacceptable time delays to the sensor output signal. Offset in a sensor is undesirable as it may limit the minimum detectable signal of the sensor. One such arrangement is described in a U.S. Pat. No. 7,425,821 entitled “Chopped Hall Effect Sensor” which issued on Sep. 16, 2008 to Allegro MicroSystems, Inc. of Worcester, Mass., the Assignee of the subject invention.
Some notch filters sample and average an input signal. A typical implementation may use two sampling stages to avoid excessive residual harmonic components. The first stage performs a sample and hold function at some time. A second stage samples the output of the first stage at a ninety degree phase shift with respect to the first stage, so as to avoid the dV/dt generated from the non-ideal sampling pulses in the first stage. The output of the second sampling stage is fed into the averaging stage, which may employ resistive averaging, multi-gate/base averaging, or charge redistribution averaging techniques. The first two approaches are continuous time approaches and charge redistribution is a discrete time approach. The continuous time approaches generally require two sampling stages, relatively large sampling capacitor sizes, such as on the order of 4-10 picofarads, and an output buffer for isolating the sampling stages from the averaging stage which may consume a significant area. This buffer stage—as well as the averaging stage—may introduce offset to the circuit. In addition the buffer stage may not be suited for dynamically cancelling its offset contribution to the circuit. The charge distribution discrete time approach uses the second sampling stage as the charge redistribution averaging stage and also requires relatively large sampling capacitor sizes, such as on the order of 4-10 picofarads, and an output buffer for isolating the capacitors holding the averaged signal from the remainder of the circuit, which output buffer may also be area consuming and not suited for using dynamic offset cancellation techniques for removing its offset contribution to the circuit.
In U.S. patent application Ser. No. 12/487,965 entitled “Switched Capacitor Notch Filter” which was filed on Jun. 19, 2009 and assigned to Allegro MicroSystems, Inc. of Worcester, Mass., the assignee of the present invention, a sampling and averaging notch filter is described in which charge from the sampling capacitors is simultaneously averaged and transferred to the filter output, thereby eliminating the need for conventional buffering between sampling and averaging stages and the associated drawbacks. However, certain response time limitations may exist due to the use of a fixed feedback capacitor.
Other notch filters sample and integrate (rather than averaging) an input signal, such as a chopped signal synchronized with the chopper clock in such a way that the unwanted ripple resulting from the chopper operation is integrated to zero over each chopper clock period. However, the accuracy of this approach highly depends on the integrating clocks phases relative to the chopper clock, and is also susceptible to the sampling non-ideal effects like charge injection and clock feed-through, such effects being reduced if averaging is used instead.
A post-filter stage may be required when using a notch filter in order to further attenuate high frequency residual components not removed (or generated) by the notch filter. As one example, the post-filter stage may be implemented with a low pass filter topology, which may consist of a resistor in parallel with a fixed capacitor in an operational amplifier feedback network. This resistor may be implemented with a switched capacitor topology to reduce the size of the circuit.